To assure high performance and good signal integrity, many issues must be considered during the design process. Designing and verifying ratio synchronous clocks rsc for highperformance. Ping yeung, chris kwok, matt berman, harry stuimer, scott wakefield, eugena talvola. Scott received a bsee from virginia tech and is now a consultant specializing in signal integrity. Here you can view and download conference andor chiphead theater presentations before, during, and after the event. Section 3 backplane architecturebackplane designers guide. Standard lownoise industrial and milgrade backplanes are used. Feasibility of extending commercial 10 gbd backplane infrastructure for use in. This application report is a revision of the original basic design considerations for backplanes, literature number szza016, published june 1999. Anisotropic design considerations for 28 gbps via to stripline transitions scott mcmorrow teraspeed consulting a division of samtec, edward sayre teraspeed consulting, a division of samtec inc.
Since design methodology of a complicated backplane system is being addressed, it is appropriate. Samtec flyover is most commonly used in midboard applications, with the cable assembly connector placed close to the chip and direct the signal to the front panel through the cable. It also facilitates concurrent design of the rest of the system by other design disciplines. The form factor was 6u and access to all slots in the rear was required in order to populate all 18 rear transition modules. The pdf of each of these imperfections has to be computed and convolved together to produce a ber margin plot. High speed channel characterization using design of experiments. System backplane for the 8231e2b, 8231e1c, 8231e1d, 8231e2c, 8231e2d, or 8268e1d approximately 15 mb saving pdf files. Designcon 2011 santa clara, california, usa volume 1 of 3.
Scott received a bsee from virginia tech and is now a consultant specializing in. Scott mcmorrow teraspeed consulting, a division of samtec design and analysis of silicone rubberbased teraposer for lpddr4 memory test bumhee bae kaist, daniel jung kaist, jonghoon kim kaist, heegon kim kaist, joungho kim kaist design and verification for highspeed ios at multiple to 60 gbps with jitter, signal integrity, and. Jan 22, 2018 designcon has been a tremendous source of information for myself and for the team i have been working with at sun microsystems, which later became part of oracle corporation. Atspeed testing of 32 gbaud pam4 interfaces using automated test equipment.
Samtec flyover is most commonly used in midboard applications, with the cable assembly connector placed close to the chip and direct the signal to the front panel through. The design process starts with laboratory measurements of the channel response. Scott mcmorrow at teraspeed consulting group a division of samtec. Design considerations for a cost optimized 28g nrz 56g pam4 backplane rula bakleh, teraspeed consulting a division of samtec scott mcmorrow, teraspeed consulting a division of samtec ed sayre, teraspeed consulting a division of samtec. Design considerations for a cost optimized 28g nrz. In the current implementation, no backplane exists and instead each dcr has a aluminum enclosure. Scott mcmorrow is an expert in highperformance design and signal integrity engineering, with a broad background in complex system design, interconnect modeling and measurement. Scott mcmorrow a highperformance package design was required for a serdestoserdes mux chip for backplane applications using eight 1.
Differential design for highspeed applications by greg. The challenge mainly lies in the extremely small current for low level gray scale. Designcon2011 santaclara, california, usa 31january 3february2011 volume3 of3 isbn. A solution for the design, simulation and validation of boardtoboard interconnects by scott mcmorrow and james bell, teraspeed consulting group, and julian ferry, samtec, inc. Pdf practical identification of dispersive dielectric models with. Scott mcmorrow, roger dame, gustavo blando, ashley rebelo, alejandro lacap, xiangyin zeng. Scott mcmorrow, president and founder, teraspeed consulting group. This type of backplane is intended for benign andor lab environments. To attain these oftenconflicting goals, it is necessary to maximize the performance of every aspect of the design, including the backplane configuration. Due to the frequencies of highperformance backplanes, transmission line behavior is common in most applications.
There is a general consensus that 10 gbps copper backplane serial links will be deployed in the near future. Accurate current signal processing technologies are employed in the design of the silicon backplane. Possible ideas on a new dcr backplane design grant hampson october 8, 2002 introduction this report describes some recent ideas on the development of a backplane for the direct conversion receivers dcr 1. The luminance of oleds is proportion to the driving current density, so proper current signals are expected to be generated for the oleds. The following is a list of common terms and definitions associated with system architecture and backplane design. A cable backplane solution for 112 gbps pam4 architecture. Oct 04, 2016 where electronics engineers discover the latest toolsthe design site for hardware software. A backplane is a multilayered printed circuit board assembly serving as the backbone of a system. If youre looking for a presentation from a specific session that youre unable to find here, it is likely because the presenter has not provided permission.
A person who plans, devises or contrives the achievement of a desired result. Silicon backplane design for oledonsilicon microdisplay. Designing dcblocking capacitor transitions to enable. This summary is an attempt to capture some of the most influential papers from the past twenty years that made the biggest impact on our work. Backplane architecture and design bert simonovichs. Jan 14, 2011 the following is a list of common terms and definitions associated with system architecture and backplane design. Pcb design and measurement, automation of signal integrity design flows, and currently focuses on system design for emerging technologies. Scott mcmorrow, president, teraspeed consulting group llc mr. Scott mcmorrow, siqual scott has 20 years system design experience in military aerospace, medical electronics, semiconductor applications, computer system design, and signal integrity engineering. Mar, 2017 scott mcmorrow, cto of samtecs signal integrity group, has developed a spreadsheet that shows, in tabular and graphical form, the differences in loss db for lengths of for megtron6 pcb materials and cable sizes from 28 awg to 36 awg at frequencies from 1 ghz to 50 ghz. Because the backplane is the key component in any system architecture, the sooner you consider the backplanes physical architecture near the beginning of a project, the more successful the project will be. Remove the five screws three from the side and two from the back that hold the backplane to the expansion unit. It is used as a backbone to connect several printed circuit boards together to make up a complete computer system.
Posts about backplane design written by bert simonovich. Design considerations for a cost optimized 28g nrz 56g. Scott mcmorrow, cto, samtec signal integrity group, walks us through a live demonstration of a cable backplane and midboard cable system, both utilizing samtec flyover. Section 3 backplane architecture backplane designers guide the primary criteria for backplane design are low cost, high speed, and high reliability. Section 4 backplane design considerationsbackplane. Practical design considerations for 10 to 25 gbps copper. Jason miller, scott mcmorrow, roger dame, gustavo blando, ashley. This paper takes a look at the practical and cost effective design aspects of the 1012. We would like to show you a description here but the site wont allow us. Thieving article thieving is still the name that fabricators use, but on a sparse board i like to think of it as copper balance like we do in packages that is used to. Electrical signaling for interconnect at 26 gbd is here pam2 for a while, for pam4 there are several chips in beta. Edn solving signal integrity problems at very high data. Mcmorrow is an experienced technologist with over 20 years of broad background in complex system design, interconnect and signal integrity engineering, modeling and measurement methodology, engineering team building and professional training.
This publication contains instructions that service providers can use to remove and replace the system backplane. Modified cots backplanes are a derivative of a cots backplane design described above. A solution for the design, simulation and validation of. Install the new backplane by reversing the procedure described in step 5 to step 10.
Practical identification of dispersive dielectric models. Semiautomatic copper foil surface roughness detection. Pathological design space advancing optimization and characterization. Section 4 backplane design considerations backplane designers guide this section focuses on designing highperformance parallel backplanes, a task that can be extremely complex. This is a backplane that features one 17 slotswide, 66mhz, 64bit compactpci bus and a reserved 18th slot, all controlled by one system slot cpu board. Scott mcmorrow is president and founder of teraspeed consulting group. Mar 10, 2017 scott mcmorrow, cto of samtecs signal integrity group, has developed a spreadsheet that shows, in tabular and graphical form, the differences in loss db for lengths of for megtron6 pcb materials and cable sizes from 28 awg to 36 awg at frequencies from 1 ghz to 50 ghz. A read is counted each time someone views a publication summary such as the title, abstract, and list of authors, clicks on a figure, or views or downloads the fulltext. High frequency design highspeed design a solution for the design, simulation and validation of boardtoboard interconnects by scott mcmorrow and james bell, teraspeed consulting group, and julian ferry, samtec, inc. By scott mcmorrow and james bell, teraspeed consulting group, and. Its purpose is to interconnect several printed circuit board assemblies called circuit packs or cards using plug in. Rula bakleh, teraspeed consulting a division of samtec.
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